Hardware accelerator to speed up packet processing in NDN router

A hardware implementation of the pending interest table (PIT) for named data networking (NDN) is presented. One of the major challenges in this research is the per-packet update requirement in NDN packet processing. In general, the data structure of the lookup table is optimized in order to minimize the implementation cost and maximize the lookup performance. However, more computation steps are required to update the highly optimized data structure. Thus, the design of the hardware lookup table needs to tradeoff between the implementation cost, lookup performance and update cost. We employ an on-chip Bloom Filter and an off-chip linear-chained hash table in our design. The lookup operation for an interest/data packet and the associated update operation are integrated into one task. This can effectively reduce the overall processing time and the I/O communications with the software control unit. Our design also incorporates a name ID table ( nidT ) to store all distinct name IDs ( nid ) in the PIT. If the content name in an interest packet can be found in the nidT , then the router needs not look up the forwarding information base (FIB) to determine how to forward the interest packet. This can reduce the workload of the FIB significantly. For proof-of-concept, the proposed hardware architecture is implemented on a FPGA and the overall packet processing rate is about 56 to 60 million packets per second. © 2016 Elsevier B.V. All rights reserved.